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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 57: GTX Transceiver PLL /Lock Time Adaptation
Symbol
Description
Conditions
Min
All Speed Grades
Typ Max
Units
T LOCK
Initial PLL lock
–
–
1
ms
T DLOCK
Clock recovery phase acquisition and
adaptation time for decision feedback
equalizer (DFE).
Clock recovery phase acquisition and
adaptation time for low-power mode
(LPM) when the DFE is disabled.
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data
present at the input.
–
–
50,000
50,000
37 x10 6
2.3 x10 6
UI
UI
Table 58: GTX Transceiver User Clock Switching Characteristics (1)(2)
Speed Grade
Symbol
Description
Conditions
-3 (3)
1.0V
-2/-2L (3)
-1/-1M (4)
0.9V
-2L (5)
Units
F TXOUT
F RXOUT
TXOUTCLK maximum frequency
RXOUTCLK maximum frequency
412.500
412.500
412.500
412.500
312.500
312.500
237.500
237.500
MHz
MHz
F TXIN
F RXIN
F TXIN2
F RXIN2
TXUSRCLK maximum frequency
RXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
RXUSRCLK2 maximum frequency
16-bit data path
32-bit data path
16-bit data path
32-bit data path
16-bit data path
32-bit data path
64-bit data path
16-bit data path
32-bit data path
64-bit data path
412.500
390.625
412.500
390.625
412.500
390.625
195.313
412.500
390.625
195.313
412.500
322.266
412.500
322.266
412.500
322.266
161.133
412.500
322.266
161.133
312.500
250.000
312.500
250.000
312.500
250.000
125.000
312.500
250.000
125.000
237.500
206.250
237.500
206.250
237.500
206.250
103.125
237.500
206.250
103.125
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes:
1.
2.
3.
4.
5.
Clocking must be implemented as described in the 7 Series FPGAs GTX/GTH Transceivers User Guide ( UG476 ).
These frequencies are not supported for all possible transceiver configurations.
For speed grades -3, -2, -2L (1.0V), a 16-bit data path can only be used for speeds less than 6.6 Gb/s.
For speed grade -1, a 16-bit data path can only be used for speeds less than 5.0 Gb/s.
For speed grade -2L (0.9V), a 16-bit data path can only be used for speeds less than 3.8 Gb/s.
Table 59: GTX Transceiver Transmitter Switching Characteristics
Symbol
F GTXTX
T RTX
T FTX
T LLSKEW
V TXOOBVDPP
T TXOOBTRANSITION
TJ 12.5
DJ 12.5
TJ 11.18
DJ 11.18
Description
Serial data rate range
TX Rise time
TX Fall time
TX lane-to-lane skew (1)
Electrical idle amplitude
Electrical idle transition time
Total Jitter (2)(4)
Deterministic Jitter (2)(4)
Total Jitter (2)(4)
Deterministic Jitter (2)(4)
Condition
20%–80%
80%–20%
12.5 Gb/s
11.18 Gb/s
Min
0.500
–
–
–
–
–
–
–
–
–
Typ
–
40
40
–
–
–
–
–
–
–
Max
F GTXMAX
–
–
500
15
140
0.28
0.17
0.28
0.17
Units
Gb/s
ps
ps
ps
mV
ns
UI
UI
UI
UI
DS182 (v2.8) March 4, 2014
Product Specification
51
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